LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
library STD;
USE STD.textio.all;
ENTITY main_tb IS
END main_tb;
ARCHITECTURE behavior OF main_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT(
p_in : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
p_out : OUT integer range 0 to 255
);
END COMPONENT;
--Inputs
signal p_in : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal p_out : integer range 0 to 255;
-- Clock period definitions
constant clk_period : time := 10 ns;
--
TYPE vector_array IS array ( 0 TO 4096) OF integer range 0 to 255;
SIGNAL memory : vector_array := ( OTHERS => 0);
signal temp : std_logic_vector(7 downto 0):= ( OTHERS => '0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
p_in => p_in,
clk => clk,
p_out => p_out
);
-- Clock process definitions
clk_process :process
variable counter : integer := 0;
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
counter := counter + 1;
IF counter > 4095 THEN
WAIT;
END IF;
end process;
process
--file in1,out1 : text;
VARIABLE my_line, out_line : LINE;
file infile,outfile : text;
VARIABLE p_in1,i,j : INTEGER;
BEGIN
file_open(infile,"in1.txt",read_mode);
file_open(outfile,"out1.txt", write_mode);
WHILE NOT(ENDFILE(infile)) LOOP
READLINE (infile, my_line);
READ (my_line, p_in1);
p_in <=conv_std_logic_vector(p_in1,8);
temp(7 downto 0) <= p_in(6 downto 0)&'0';
memory(i) <= conv_integer(unsigned(temp)); --stopped
i := i+1;
WAIT FOR 10 ns;
END LOOP;
----
WHILE j < 4095 LOOP
WRITE (out_line, memory(i));
WRITELINE (outfile, out_line);
i := i+1;
WAIT FOR 10 ns;
END LOOP;
WAIT;
END PROCESS;
END behavior;