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why I have this fatal error?

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JKR1

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I wrote the following code for shifting the intensity of each pixel one to left,
but I have a fatal error and stopped at the line the I specified...
I dont know my testbench is right or not,first time writing testbench for image processing,its just succesfully compiled,i would appreciate if aware me of existing mistakes.
image is 64*64=4096
tnx
code
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_arith.ALL;
use IEEE.NUMERIC_STD.ALL;

entity main is
port(p_in : in std_logic_vector(7 downto 0);
clk : in std_logic;
p_out : out integer range 0 to 255);
end main;
-----
architecture main_arch of main is
signal temp : std_logic_vector(7 downto 0);
BEGIN
PROCESS(clk)   
BEGIN
IF (clk'event AND clk = '1') THEN
temp <=  p_in(6 downto 0)& '0';
p_out <= to_integer(unsigned(temp));
END IF;
END PROCESS;
END main_arch;
testbench:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;

library STD;
USE STD.textio.all;
 
ENTITY main_tb IS
END main_tb;
 
ARCHITECTURE behavior OF main_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT main
    PORT(
         p_in : IN  std_logic_vector(7 downto 0);
         clk : IN  std_logic;
         p_out : OUT  integer range 0 to 255
        );
    END COMPONENT;
    

   --Inputs
   signal p_in : std_logic_vector(7 downto 0) := (others => '0');
   signal clk : std_logic := '0';

 	--Outputs
   signal p_out : integer range 0 to 255;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
	--
	
  TYPE vector_array IS array ( 0 TO 4096) OF integer range 0 to 255;
  SIGNAL memory : vector_array := ( OTHERS => 0);
  signal temp : std_logic_vector(7 downto 0):= ( OTHERS => '0');

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: main PORT MAP (
          p_in => p_in,
          clk => clk,
          p_out => p_out
        );

   -- Clock process definitions
   clk_process :process
	variable counter : integer := 0;
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
		counter := counter + 1;
     IF counter > 4095 THEN
     WAIT;
    END IF;
   end process;
	
	
	process
    --file in1,out1 : text;
    VARIABLE my_line, out_line : LINE;
    file infile,outfile : text;
    VARIABLE p_in1,i,j : INTEGER;
   
     BEGIN
    
   	file_open(infile,"in1.txt",read_mode);
    file_open(outfile,"out1.txt", write_mode);
    
    WHILE NOT(ENDFILE(infile)) LOOP
      READLINE (infile, my_line);
      READ (my_line, p_in1);
      p_in <=conv_std_logic_vector(p_in1,8);
		  temp(7 downto 0) <= p_in(6 downto 0)&'0';
		  memory(i) <= conv_integer(unsigned(temp));  --stopped
		  i := i+1;
      WAIT FOR 10 ns; 
      END LOOP;
		----
	  WHILE j < 4095 LOOP
	    WRITE (out_line, memory(i));
      WRITELINE (outfile, out_line);
	    i := i+1;
      WAIT FOR 10 ns;
      END LOOP;
      WAIT;
      END PROCESS;
  
END behavior;
 

FvM

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There's always a clear error mesage telling you why the simulator stopped. I guess index i out of range.
 

JKR1

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Capture.PNG
this is the error,its not clear:sad:
 

std_match

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You have an array 0 to 4096, should probably be 0 to 4095.
The line "WHILE j < 4095 LOOP" is probably wrong.
j is never set. The test should be <= 4095.

Do you have too many lines in the file in1.txt ?
 

JKR1

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i have an image 64*64 and the pixels are in text file 4096 line,i define it 0 to 4095,
i want to write each pixel with j,i changed the loop with 4096 but the error didnt change
 

FvM

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I don't believe that you don't get additional info along with the "fatal error". But even if you don't, there's a lot of possibilities to find out what's going on, e.g. to check in which iteration of the loop the error is asserted.

The error is probably brought up because you missed to initialize variable i.
 
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JKR1

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I did some changes ,I dont have fatal error,but when I open the output file 'out1.txt' all the 4096 pixels are 0.:sad:
Code:
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

library STD;
USE STD.textio.all;
 
ENTITY main1_tb IS
END main1_tb;
 
ARCHITECTURE behavior OF main1_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT main1
    PORT(
         p_in : IN  std_logic_vector(7 downto 0);
         clk : IN  std_logic;
         p_out : OUT  integer range 0 to 255
        );
    END COMPONENT;
    

   --Inputs
   signal p_in : std_logic_vector(7 downto 0) := (others => '0');
   signal clk : std_logic := '0';

 	--Outputs
   signal p_out : integer range 0 to 255;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
	--
	
  TYPE vector_array IS array ( 0 TO 4096) OF integer range 0 to 255;
  SIGNAL memory : vector_array := ( OTHERS => 0);
  signal temp : std_logic_vector(7 downto 0):= ( OTHERS => '0');

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: main1 PORT MAP (
          p_in => p_in,
          clk => clk,
          p_out => p_out
        );

   -- Clock process definitions
   clk_process :process
	variable counter : integer := 0;
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
		counter := counter + 1;
     IF counter > 4095 THEN
     WAIT;
    END IF;
   end process;
	
	
	process
    --file in1,out1 : text;
    VARIABLE my_line, out_line : LINE;
    file infile,outfile : text;
    VARIABLE p_in1,i,j : INTEGER := 0;
   
     BEGIN
    
   	file_open(infile,"D:\IP\in1.txt",read_mode);
    file_open(outfile,"D:\IP\out1.txt", write_mode);
    
    WHILE NOT(ENDFILE(infile)) LOOP
      READLINE (infile, my_line);
      READ (my_line, p_in1);
      p_in <=conv_std_logic_vector(p_in1,8);
		  temp(7 downto 0) <= p_in(6 downto 0)&'0';
		  memory(i) <= conv_integer(unsigned(temp));  --stopped
		  i := i+1;
      WAIT FOR 10 ns; 
      END LOOP;
		----
	  WHILE j < 4096 LOOP
	    WRITE (out_line, memory(i));
      WRITELINE (outfile, out_line);
	    j := j+1;
      WAIT FOR 10 ns;
      END LOOP;
      WAIT;
      END PROCESS;
  
END behavior;
 

FvM

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I think you should start to use the debugging features of the simulator. Inspect variables and signals during execution.
 
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JKR1

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how can I use it?"the debugging features of simulator"
 

dpaul

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Every simulator has a "Help" tab, clearly visible somewhere near the top-middle part of the simulator main window. Click there, spend some time reading the help files. In at least one of them there will be clear pictorial indications on how to use the simulator tool.
 

FvM

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I thought particularly of monitoring data in a list or waveform viewer, inspecting memory objects or trace sequential code execution.
 

dpaul

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Yes, correct! Assuming the OP is a newbie, I intended to make him aware where of where to find help in general for all types of simulator issues.
 
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