The constrain is determined according to the requirement of design. So, it should be decided by people...
For digital circuits, the timing must meet the corresponding requirement otherwise the results from the circuit will be erroneous.
sdf can be used to check the functionality of the circuits.
For many digital designers, if the digital circuits are not so big or/and don't have interface with other big circuits, they just roughly estimate the sdc. Timing analysis accuracy seems not so important for them.