Why does this net have such a big delay while it has only one fanout?

[alexhugo]

Hi,

In following timing report (generated by "report_timing -nets -capacitance -nworst 10"), output (ZN) of U65427 has 160.79ns delay.
You can see this instance has one load (fanout).
I need to find the reason for this big delay and resolve it. Also why library setup time is so huge?

Design size is 5 million gate.(160ns seems to be too big even for 5million gate).
Library is 40nm and I am using dc_shell version H-2013.03-SP1
Clock and reset are constrained not to be touched.

I made the report to be an image to read it easier. It is in



I ran a report_net on that wire and following is the result. As you can see it has one load and the capacitance is 0.0004317. This capacitance is the same size like other nets.

***************** REPORT_NET *********************
net 'node_3/N49059':
dont_touch: TRUE
pin capacitance: 0.0004317
wire capacitance: 0
total capacitance: 0.0004317
wire resistance: 0
number of drivers: 1
number of loads: 1
number of pins: 2

Connections for net 'node_3/N49059':

Driver Pins Type Pin Cap
------------ ---------------- --------
node_3/U65427/ZN Output Pin (OAI22D0BWP) 0

Load Pins Type Pin Cap
------------ ---------------- --------
node_3/index_reg[103][4]/D Input Pin (SDFQND0BWP) 0.0004317



Any help is appreciated.
Alex

************** REPORT_TIMING ********************
Point Fanout Cap Incr Path
------------------------------------------------------------------------------------
clock mck (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
node_23/out_to[18][3][0]/CP (SDFQD4BWP) 0.00 # 0.00 r
node_23/out_to[18][3][0]/Q (SDFQD4BWP) 0.05 0.05 r
...
...
node_3/n163296 (net) 2 0.00 0.00 0.65 r
node_3/U120123/ZN (ND2D2BWP) 0.02 0.66 f
node_3/n163293 (net) 7 0.00 0.00 0.66 f
>>>>>> node_3/U65427/ZN (OAI22D0BWP) 160.12 160.79 r
>>>>>> node_3/N49059 (net) 1 0.00 0.00 160.79 r
node_3/index_reg[103][4]/D (SDFQND0BWP) 0.00 160.79 r
data arrival time 160.79

clock mck (rise edge) 2.50 2.50
clock network delay (ideal) 0.00 2.50
node_3/index_reg[103][4]/CP (SDFQND0BWP) 0.00 2.50 r
library setup time -127.94 -125.44
data required time -125.44
------------------------------------------------------------------------------------

data arrival time -160.79
------------------------------------------------------------------------------------
slack (VIOLATED) -286.22

 

[mail4idle2]

what is that cell functionality, as it also matters

 

[rca]

It seems the tool used a very low drive cell, no?
could you report also the slew value seen at the inputs of this U65427 cell.
remember the timing table is function of the output load and the input slew.
it is usefull to report "derate factor", "slew", input & output pin, to have the delay due to net and cell separated.

 

[alexhugo]

I set some cells not to be used and the delay in the path is gone but the library setup time is still huge.
This is new report with more information.
I really don't know how the library setup time can be this big

 

[rca]

is there a false path on this net?
define as clock net?
used for scan nets?

 

[pavanks]

Can u also check the transition on the clock pin ?

 

[kck_246023]

calculate net delay
cell delay
source drive strength
sink drive strngth
clock transition

 

[yx.yang]

big transition --> big setup requirement --> violation.
You need check why there is some big transition. Maybe SI problem, or some problem in the extracted RC file.

 

[kornukhin]

Try to check your Liberty files. It is possible they have characterization issues. Compare delay values for some cells (ex., OAI22D2BWP vs. ND2D2BWP, or SDFQD4BWP vs. SDFQND1BWP). Also check that all Liberty files has same units.