Why do we fix load and slew violations?

[ukint]

Hi,
Can someone explain why we have to fix load and slew violations even after the timing is clean?

Thanks,
Vivek

 

[dick_freebird]

Static timing has no clue about things like trace couplings that
could (say) make an inverter reswitch when a slow moving input
is modulated by a sharp coupled transition. Plus timing characterization
is performed across a fixed range of load and input risetime,
and rules "keep you inside the map".

The digital paradigm is one of abstraction and constraint.
You don't get to only believe the abstraction.

 

[ukint]

Thanks for the reply. Can you elaborate more on your reply. I am not able to understand it completely.
So are you suggesting that the STA tool doesnot model the max trans and max cap correctly?

 

[dick_freebird]

It only models what it is given. Whoever did the cell library chose
a range of risetimes and loads to characterize and build the
timing model tables (or functions) from. This is your "known space".
Complementary to this are a set of hard constraints, the "fence" you
can't go outside and believe the STA timing closure.

What STA (static) can't deal with, is dynamic effects such as the
next wire over, which STA treats as a simple shunt capacitance,
switching at exactly the wrong time and advancing a clock
or retarding data or creating a timing hazard / spike where there
would have only been slowness.

If you work with comparators you know about how a slow input
risetime enables output chatter based on small amounts of
input noise. Your "chatter window" is the transform of input
signal slope and input "linear window" (roughly (VOH-VOL)/gain).