nxthuan512
Newbie level 3
Hi,
I am working on the full digital implementation using Synopsys/Cadence tools.
The implementation steps include: (1) Synthesized by Design compiler -> (2) Simulated netlist by VCS -> (3) Place&Route by IC Compiler -> (4) Simulated ICC file by VCS -> (5) DRC/LVS/Antenna check by Calibre -> (6) Simulated spice file of LVS by nanosim -> (7) Extracted C and RC by starrc -> (8) Simulated C extracted file by nanosim -> (9) Simulated RC extracted file by nanosim.
Steps (1) to (8) delivered correct results (log files) and waveform. The simulation results of LVS and C extraction were also correct. However, the simulation results of step (9) was incorrect.
Could you please give some solutions for this problem, e.g. what step should I check again etc.
Thank you very much
I am working on the full digital implementation using Synopsys/Cadence tools.
The implementation steps include: (1) Synthesized by Design compiler -> (2) Simulated netlist by VCS -> (3) Place&Route by IC Compiler -> (4) Simulated ICC file by VCS -> (5) DRC/LVS/Antenna check by Calibre -> (6) Simulated spice file of LVS by nanosim -> (7) Extracted C and RC by starrc -> (8) Simulated C extracted file by nanosim -> (9) Simulated RC extracted file by nanosim.
Steps (1) to (8) delivered correct results (log files) and waveform. The simulation results of LVS and C extraction were also correct. However, the simulation results of step (9) was incorrect.
Could you please give some solutions for this problem, e.g. what step should I check again etc.
Thank you very much