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To be precise for CMOS static power consumption is less...CMOS as u know is a combination of NMOS and PMOS...which governs the vdd and gnd respectively...due to which power is consumed only during transition state..
first of all in mos,power is negligibly consumed in steady state(after switching),compared to say bjt where power is consumed even during ON times as mostly the bjts are not allowed to fully saturate to reduce switching time. Again current thru mos is directly related to width to length ratio of channel.This can be suitably scaled to reduce current, hence power consumption. In CMos the largest contributor to wastege of power is dynamic charging/discharging of mos capacitor.
how do you say so... even in a simple CMOS inverter there is a direct path between Vdd and Gnd....
As far as i know by reduction in size the power supply rail and hence the power consumption is reduced to form low power CMOS.... please clarify my doubt....
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