Why are there many types of dummy layers for real one?

[naruhwa]

Hi all,
I have a question about dummy layers, ex: dummy metal. I am working on 28nm technology and I see there are many type of dummy layer for real one. Example: metal 1 has 4 to 5 dummy layer for it, so why do we use many type of them?
Please help me to explain it
Thanks in advance

 

[dick_freebird]

Probably not "dummy" but rather special purpose.
Like you may see met1_vdd and met1_vss in a kit
which will all be "ORed" with met1 at mask fab prep
but during design, enable a very simple "power short"
check by DRC (provided you stuck to the discipline)
that later LVS would flag, but give no help in locating.
Maybe a met6_ind layer would be used to assert
special rules for inductor design. And of course you
have the "extracted" purpose used as an intermediate
step in building connectivity netlists, etc. There may
be a true "dummy" (pattern fill) as well that helps with
that bit of drudgery, building and/or checking density
and maybe avoiding specific circuit features.

Advanced nodes have kooky lithography and mask
generation "stuff" that makes no sense to the regular
designer. Some (sub-)layers may be specific to that,
trying to keep you from -having- to understand and
manipulate that non-circuit data.

I'd bet that all of this is described somewhere in
the PDK document-mound.

 

[naruhwa]

Thank you for your answer, dick_freebird
I have read and searched many with google and design rule manual but I am not clear about this.
I made layout for my cell and in final phase of this process, I used a tool of calibre to auto fill metal into my layout.
I see tool add dummy layers into layout, ex: metal 1 has 4 "special" layers, in higher metal as metal 4,5,6, they also add dummy metal and dummy OPC. I know OPC is a process to correct mask in fabrication.
My question is why we need OPC dummy if we had dummy metal?
Pls help me with this.
Thanks so much