Why are Synopsys Fusion Compiler reference methodology scripts fail on a single module verilog: Design has no site rows or site arrays.

[unixdaemon]

I am using a simple single module verilog with Synopsys FC-RM_U-2022.12 scripts.

The init_design stage fails:

RM-info: init_design touch file was not created due to potential issues found in "Basic floorplan and design checks" section. Please check RM-error messages in the log.

Earlier in the log the 'Basic floorplan and design checks' failed:

RM-error: Design has no site rows or site arrays. Please fix it before you continue!
RM-error: Design has no signal terminals. Please fix it before you continue!
RM-error: Design has no tracks. Please fix it before you continue!
RM-warning: Design does not contain any PG shapes. You do not have proper PG structure. If this is unexpected, please double check before you continue!
RM-warning: Design has no boundary or tap cells. If this is unexpected, please double check before you continue!

What are "site rows" and "site arrays"? Why do RM scripts expect them? What are "signal terminals", "tracks" and "tap cells"?
How to fix all these errors?

The verilog that I am trying to compile:

module few_logic_ops
#()
(wire1, wire2, wire3, wire4, wire5);
input wire wire1;
input wire wire2;
input wire wire3;
input wire wire4;
output wire wire5;

assign wire5 = (wire1 & wire2) | (wire3 & wire4);
endmodule