Why are fractional spurs a problem in ADPLL?

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vamshi990

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I would like to know why fractional spurs are more of a problem in All digital PLL when compared to more traditional charge pump PLLs. I'm guessing it must be because of the sampling nature of the TDC . Are the fractional spurs that fall beyond the reference frequency folded back due to aliasing? Any references with detailed analysis of this or explanation would be great!

Thanks,
 

some specialist on PLLs? help!
 

If you are referring to a phase detector that is a straight digital PWM voltage chop there will be more reference spur component that the loop filter must attenuate then a current source charge pump phase detector.

Tristate phase detectors provide even less reference component to filter but you have to be careful of tristate control hole float near zero phase lock conditional. This is where there is no change from tristate output for small degree angles of two input signals to phase detector. The solution is usually to provide some intentional leakage via a bleeder resistor or bleeder current source on detector output to force the lock condition to alway provide some small correction output.
 

Thanks RC, but can you elaborate on digital PWM chop? I don't exactly know how that works and googling wasn't of much help either!
In my question I meant some kind of a time to digital converter that quantizes the input time differences in terms of the number of fixed time delays, lets say an inverter delay. When I was referring to some papers on All digital PLLs I find that the spurs are much worse than in a standard charge pump PLL. So I am trying to understand what makes the digital version that bad? Is it just because of the quantization noise that is inevitable when one goes from A/D (here time to digital) and D/A (Digitally controlled oscillator) domains? or is there some other reason?
 

The simplest PWM chopper would be using an EXOR gate for the phase detector. Lock on this is at 90 degs phase difference. Other version more complex are D-edge triggered flip flop phase detector.
 

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