Who's goin to dominate the nex-generation HDL world?

[roger]

ghdl verilog systemverilog

Verilog2001
System Verilog
VHDL
System C

who's going to be the winner?
share your idea with me 8)

 

[jimjim2k]

ghdl systemverilog

Hi

this is a multi-fold problem


1. Vendors spect
2. Tools aspect
3. Languages aspect


1. From the vendors aspect the following theory guides you

Jimjim2k Theorem 1
Theorem: In the Domain (V) of Vendors, there are at least three vendors with the following conditions:
Vendor V1 (in a subject SSS) is major in customers and development team and Market
Vendor v2 (in the same subject SSS - note that it is spelled in lower case) is major in inventions and breaking ideas.
Vendor V3 (in a subject sss note that it is spelled in lower case) is major in customers and development team and Market . V3 is in race with V1.

Then the steady state of the competition of V1 and v2 in presense of V3 is either of the following possibilities.

Possibility 1: Winner is V1 = V1 U v2
Possibility 2: Winner is V3 = V3 U v2 results in V3 > V1
Possibility 3: Winner is GPL= {v2 puts the idea as open cores under GPL}

Note 1: The porobability is differs from the possibility here.

Sample example:

V1: Synopsys
v2: avanti
V3: Cadence
SSS: Simulation, Verification and EDA.
Possibility 1: V1 = V1 U v2
Result in fact: Synopsys now have HSPICE and NANOSIM both together.



2. Tools aspect

From The Tools aspect I think the following Theorem guides you

Jimjim2k Theorem 2
Theorem: In the Subject SSS the following conditions are satisfied:

Tool T1 is used for task T1 from approach A1
Tool T2 is used for task T1 from approach A2
Tool T3 is used for task T1 from approach A3
Tool set TS1 is exists for cross-compilation CS1 (OS1-OS2-OS3)
Tool set TS1 handles all approaches of A1, A2, and A3.

The steady state Tool for subject SSS is Tools T as

T = TS1 U {T1, T2, T3}


Example:
T1: Verilog HDL in Linux
T2: VHDL HDL in Windows
T3: SystemVerilog in Solaris
TS1: Tcl/Tk

T = Modelsim

3. Languages aspect

Jimjim2k Theorem 3
Theorem: There are a finite set fo languages as:

Language L1 with feature set FS1
Language L2 with feature set FS2
Language L3 with feature set FS3

FSi (i = 1, 2, 3) include PLI or DPI ( if you are un-familiar with HDL please seek for your-self)

Now in the steady-state a virtual language VL is results as:

VL = U(FS1(L1), FS2(L2), FS3(L3)

Example:
L1: Verilog
L2: VHDL
L3: SystemVerilog

VL = U(Verilog, VHDL, SystemVerilog)

Actual examples:

Modelsim VL supprts all of Verilog, SystemVerilog, systemC, ...
Metors AMS supports mixed-signal modeling and simulation




Best Regards
Jimjim2k

 

[ramesh]

Forgot to mention Handel-C ....!

 

[roger]

Hi jimjim2k
Good answer, would you talk more about the new capability.
It seemed that the VHDL HDL lack of the PLI & didn't improve.
Am I wrong? 8)

 

[efundas]

I think we need some common language and environment which can be used right from design phase to system level validation. ie, code the design in language X, develop the test environment in language X, interface that supports the usage of already developed test environment in language X to be used in system level validation. Till then languages such as SystemC, SystemVerilog etc will be coming and going

 

[roger]

It's said that synopsys is going to abandon SYSTEMC
Is that true?

 

[zwj_seu]

I think systemverilog is best!
It could be used as design and verification language!

 

[wadaye]

It's said that synopsys is going to abandon SYSTEMC
Is that true?

Yes they will abandon SYSTEMC and high_level synthesis tool(Behavior Compiler).

I think SystemVerilog will be the winner, because the better Synthesis

and Verification ability than verilog and VHDL. But this will not very soon,

it seems the EDA tool support for SystemVerilog not very strong now. It's

need time to support it.

wang1

 

[alex king]

I think system verilog will be succeed!

 

[omara007]

i guess SystemC and similar C based system design languages will have a good future if EDA tools companies work on synthesizing them into Hardware ..
Yet .. i beleive their can be another direction .. which is to take the HDL like VHDL and Verilog to the software pool .. why not being able to write an executable program in VHDL ? .. if this happens , it will result in a language that fuses the barrier between SW and HW .. and partitioning decision won't be any hard ..

But who works on this stream !!

 

[jasmain]

I think system verilog is more convicing,for it not only can use to system level but also can be synthesised.
most of all,it is good for testbench.

 

[omara007]

i have heard that there is some kind of work to make VHDL an OOP language .. anyone has any idea about that ?

 

[the_penetrator]

GHDL (at ghdl.free.fr) offers much promise on building executables for VHDL designs.

It is built on GCC.

the_penetrator©

 

[radix]

omara,

VHDL already has some OOP features like operator overloading and polymorphism.

 

[omara007]

I don't mean OOP features as much as I mean compiler-wise .. in other words .. to get an executable ahead-of-time program out of ur VHDL code ..

 

[beta0]

system verilog ,maybe.

 

[yangvic]

I like Verilog anyway.language is just tool.The key is how to implement your logic by this tool.

 

[roger]

Today, people talk about system-level verification,
I don't quite understand the meaning of system level.
That's not the point, from my perspective, the simulation time's the point.
We have verilog or VHDL, which can perfectly modeling the behavior of
hardware, we have obj code, which's exactly the compiled result.
and the software environment like 8051 , ARM are so mature.

What will we gain by so called" both hardware & software using same language or same platform"? speed ? accuracy? I doubt.

 

[galant]

The system level verification is performed to check the architecture against the intended functional and performance requirements.
There are some EDA tools for system level verification ,such as vera, systemc,system verilog. I think systemc is most popular now.

 

[sifeddin]

I think the language that will include the analog circuit description, verification and synthesis will eventually win the race as there is no chance we outcast the analog signal from the world we live in regardless of how fancy our digital processors we build.