If you use timer or counter , the pulse is like __________
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if adder , you will get ___ ___
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Sorry , the previous one's position
is shifted, So I redraw it.
__________
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|__________,
if adder , you will get
___ ___
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____| |___| |____ ............
Hi cyteng,
I agree that both way will produce a pulse width modulation but the first choice is, as far as I know, the one that is mostly used.
junchaoguo51888,
go to xilinx web site and search for PWM. They published a paper some time ago (you can get the vhdl code too) which is basic but might help you.
I've done a little about PWM with FPGA,I've used counter and the result is satisfying.While I have no idea of the second choice which is provided by cyteng,