For verification:
“Assertion Based Design” by Harry Foster
“Principles of Verifable RTL Design” by Lionel Bening, Harry Foster
“Writing testbenches” by Janick Bergeron
“Verification Plan: The Five-Day verification …” by Peet James
'The art of verification with VERA', by F. Haque, K. Khan and J. Michelson.
For design:
“Reuse Methodology Manual” by Michael Keating
“ASIC … the book” by Michel Smith
articles from
www.sunburst-design.com and
www.deepchip.com
Synopsys Workshops and documentation
Verilog LRM
Notice that:
- there are no good Verilog or VHDL book, all of them are written to take some money and cover much less then Verilog LRM, don’t explain anything about verification and nothing about backend process (Smith’s book is exception but it is from 1995)
- there are no good book which help with synthesis, static timing analysis, and Synopsys documents and Workshops are better then anything you could find
- there are no book which cover using of Perl and makefiles in building of verification, sythesis or backend environments