Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Who can explain the difference between clock and reset tree?

Status
Not open for further replies.

openwindows

Junior Member level 3
Joined
Jan 18, 2002
Messages
28
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
102
clock tree/reset tree

who can explain the difference of between clock tree and reset tree?
 

jkfoo

Member level 1
Joined
May 17, 2001
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
261
well, what i did was, select appropriate buffers for those nets, i mean clock-tree buffer for clocks and reset buffer of reset (depends on asic vendors), set_dont_touch on those nets during synthesis. Proceed as per normal for post synthesis flow.
 

CRiSP

Full Member level 2
Joined
May 28, 2001
Messages
122
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
577
difference

whta is difference ??????????????????
 

jkfoo

Member level 1
Joined
May 17, 2001
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
261
i don't think they make any difference from the synthesis point of view. but i am not sure when it comes to post synthesis flow, perhaps just a technique to differentiate between the clocks and the reset signals.
 

roli

Full Member level 5
Joined
Apr 29, 2001
Messages
246
Helped
9
Reputation
20
Reaction score
9
Trophy points
1,298
Location
'SiliconWafer' Island
Activity points
1,824
The issue here is NOT the mechanics or semantics of Synopsys.

There is a major difference between Clock Tree & Reset Tree - in regards to correct design practices.

1. Clock Tree must always be 'Skew Balanced' to avoid synchronous skips & races.
2. Reset Trees - especially for those cases where the Reset is Asynchrounous - MAY not be 'Skew Balanced' (in most of the times).
3. Reset Tree can be MORE loaded than Clock Tree - e.g. - a relaxed DRC rule cab be set for Reset Tree - since Flip-Flops unstable behavior is less sensitive for slow slew rates in the Reset input (while the Clock input is).
4. Some ppl consider synchronizing the Reset input signal with the main System Clock. While this is a correct practice to avoid Metastability at the trailing edge of Reset, some skew problems may arise. For those cases, carefull STA must be run to alert the designer.
 

jkfoo

Member level 1
Joined
May 17, 2001
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
261
thanks for your info, i learned a great deal from that. One question, what is the point of using reset tree if they are not "Skew Balanced". Perhaps, if your design will always go to a known state after an asynchronous reset, then you will avoid the risk of getting into metastability. State-machine design is a good example.
 

papertiger

Member level 2
Joined
Dec 28, 2002
Messages
52
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
319
reset is much more loose

jkfoo said:
thanks for your info, i learned a great deal from that. One question, what is the point of using reset tree if they are not "Skew Balanced". Perhaps, if your design will always go to a known state after an asynchronous reset, then you will avoid the risk of getting into metastability. State-machine design is a good example.
Clock skew is related to chip speed while reset is not.

clock tree may set to 300ps skew with 500 ps transition time while
reset may only require 1000/1000.
 

roli

Full Member level 5
Joined
Apr 29, 2001
Messages
246
Helped
9
Reputation
20
Reaction score
9
Trophy points
1,298
Location
'SiliconWafer' Island
Activity points
1,824
You need a Reset Tree to reduce heavy load.
But Skew requirements for reset trees are almost non-existent for Asynchronous Resets !
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top