Which tool do RTL to gate level?

[sc266]

Hi! everyone,

I'm newbie in ASIC. Can I see the gate level by using NCVerlog and IUS from Cadence? The reason is that I want to layout a simple flip flop after I write verilog and simulate by using NCVerilog, check logic but I can't find or see the gate level in order to layout. Can someone correct me if I'm wrong oe which should I need to go to the target?
Thanks

 

[pintuinvlsi]

RTL to gate level

RTL to gate level is done by Synthesis tool like DC compiler. Again in FPGA tools you can see RTL to gate level. Even i think if you have modelsim there you can see that.

Hope this answers your queries.

Regards,
pintuinvlsi

 

[alok_msh]

Re: RTL to gate level

if you have novas design. Debussy/verdi can also be used to get the schematic representation based on RTL

 

[sc266]

Re: RTL to gate level

Hi

Is synopsys_VCS or Primetime can see the gate level from RTL? Which version of synopsys is compatible to cadence IC5141?

Thanks

 

[avimit]

Re: RTL to gate level

Dear dear,
pls can you elaborate: what do you mean by "see"
Also this link may help you:
**broken link removed** ( look for Introduction to digital ASIC design on this page)

 

[funzero]

Re: RTL to gate level

modelsim can view schemetic in his tool

 

[satyakumar]

Re: RTL to gate level

Hi sc266,
In ASIC flow RTL to gate's conversion is done through synopsys design compiler, this step is necessary when u want to do layout for your design. And simulators at gate level can be used for doing timing simulation, for viewing schematic simulator is not necessary. In DC it will show complete schematic of your design interms of gate's.
Xilinx also will show gate level, but its target implimentation is only in fpga.
Hope this clear your doubts.

regards
satyakumar