Re: RTL to gate level
Hi sc266,
In ASIC flow RTL to gate's conversion is done through synopsys design compiler, this step is necessary when u want to do layout for your design. And simulators at gate level can be used for doing timing simulation, for viewing schematic simulator is not necessary. In DC it will show complete schematic of your design interms of gate's.
Xilinx also will show gate level, but its target implimentation is only in fpga.
Hope this clear your doubts.
regards
satyakumar