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Which std logic code is better ?

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vlsi_freak

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Which one would you use and why?

I vote for the first method???


signal a_sig : std_logic_vector(n downto 0);
signal b_sig : std_logic_vector(n downto 0);

process(a_sig,bsig)
variable c_sig : std_logic_vector(n downto 0);
begin
c_sig := a_sig-bsig;
a_is_smaller <= c_sig(c_sig'high);
end process;

process(a_sig,bsig)
variable c_sig : std_logic_vector(n downto 0);
begin
if(asig < bsig) then
a_is_smaller <= '1';
else
a_is_smaller <= '0';
end if;
end process;
 

lordsathish

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Re: Which one is good

I think the answer to your question depens upon the synthesis tool that you use...the less than comparator might have less number of gates than the subractor... so i guess the second code will be better...
 

gck

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Re: Which one is good

First approch is just taking one substractor and second approch is taking comparator.

First approch is taking less combinational delay than second one. So I will also go for First approch.
 

ameed

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Re: Which one is good

hi,

depends on synthesis tool.

thanx......
 

    vlsi_freak

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