my experience
Hi, I have not used a STD gating cell from ASIC vendor, but I have tried to use a integrated-gating-cell(Latch, posedge) that created by our circuit design team. Power compiler seems can not handle the cell very cell, I hope DC to replace my clock enalbe flip-flop by puting a gating cell in front it and replace the flip-flop with no clock enable pin. DC do insert the gating cell, but do not replace the clock enable flip-flop. This is quite strange. My work around is insert clock gating circuit using std cells, then hack the netlist by a perl program. The chip do works.