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Synopsys Power Compiler can use integrated gate-clock cell (Latch type) to implement a low power design. Which StandCell Library support the integrated gate-clock cell (Latch Type) that can be used by power compiler ?
I did know that DC with power compiler feature can handle gate clock circuit without integrated gate-clock cell in standard-cell library. And, I did know how to implement the Gate clock funtion(using VHDL/Verilog) with DC (no power compiler feature). For some reason , I still want to know :
Which StandCell Library support the integrated gate-clock cell (Latch
Type) that can be used by power compiler ?
Hi, I have not used a STD gating cell from ASIC vendor, but I have tried to use a integrated-gating-cell(Latch, posedge) that created by our circuit design team. Power compiler seems can not handle the cell very cell, I hope DC to replace my clock enalbe flip-flop by puting a gating cell in front it and replace the flip-flop with no clock enable pin. DC do insert the gating cell, but do not replace the clock enable flip-flop. This is quite strange. My work around is insert clock gating circuit using std cells, then hack the netlist by a perl program. The chip do works.
There are no serious problem with testability (of course we have a few ATPG untestable points in clock-gatted-cell, but it is not important because this number is small).
In scan mode, this gated clock is replaced with scan clock.