HI
SV in designing is just now only picking up its pace. only DC will synthesize the SV and i am not comp
letly sure whether it supports all the constructs or not (for designin)
Hi,
I know that ModelSim supports most of the SV stuff - whether its design or verification- and you can check the TechNotes to know to what extent is the SV supported.
ModelSim PE student Version (Free Version) : SV design and Verification (Parts ; Assertion Based Verification and other features aren't supported)
ModelSim SE : SV design and Verification.
HI
SV in designing is just now only picking up its pace. only DC will synthesize the SV and i am not comp
letly sure whether it supports all the constructs or not (for designin)
I know that RTL Compiler (RC) from Cadence supports SV for Synthesis. Also Synplicity has basic support and is increasing.
On the simulator side every major vendor has support for it quite well now. VCS, Questa, NC, Rivera from Aldec. MPSim from Axiom is also adding SV support.
Haha, no. Synopsys VCS is perhaps the gold standard of Systemverilog simulators. It had the most Systemverilog coverage (of the big 3 vendors: Cadence, Mentor, Synopsys) for a long, long time.
Only now, has Cadence Incisive caught up to a competitive level. (Modelsim+Questa were ahead of Incisive for the past year.)