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VCS 7.1 only supported systemverilog 3.0 ie. the design portion only. VCS 7.2 will support sv3.1a ie. the verification portion and VCS7.2 should be releasing within these few days.
VCS 7.2 still doesn't support System Verilog Testbench
(the full 3.1a spec). Will that feature be on its way shortly, or is
Synopsys going to emphasize the VCS-exclusive NTB for the future?
I would go even further to say that most Verilog simulators still don't have 100% Verilog-2001 support. But they've come a long way since 3 years ago, and it seems that the major vendors have implemented the most useful/requested features of Verilog-2001.
I assume the adoption of SystemVerilog will proceed along a similar path/rate. Systemverilog is a bigger upgrade (to Verilog-2001) than Verilog-2001 was to Verilog-1995.
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