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Which signals should be included in the process sensitivity list ?

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Nikolai

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I have a fairly basic doubt here...

Is there a particular rule as to which signals to include in the process sensitivity list

eg :

process (CLK, clkDiv)
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;


this was taken from digilent's UART example... I see no reason why "clkDiv" was included in the sensitivity list, since signal assignments take place only on
"CLK" events.
 

kishore2k4

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Re: Sensitivity list

Generally speaking, all variables that are used on the right side of an assignment expression should be in the sensitivity list. In your case it is
clkDiv <= clkDiv +1;
 

Nikolai

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Re: Sensitivity list

But even if "clkDiv" wasnt included in the sensitivity list, its wont make any difference since there must be an event on CLK first for the process to proceed....

Similarly in the D flip flop example...

if reset is asynchronous then it must be in sensitivity list...
but if reset is sync then i believe it shouldnt be in sensitivity list...
 

Kazzam

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Re: Sensitivity list

hi,
as far as my knowledge, a clock is an event, i.e. time taken by a signal to change in a given time span,
and clk div is used for the purpose of incrementing and decrementing the count..........
in other words it is used as a counter.
so being the purpose of clk'div being used

regards
kazzam
 

avimit

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Re: Sensitivity list

Hi
Rest assured that what u say is right.
the use of clkDiv in sensitivity list is redundant, and may have been included by mistake.
No use of it in the sensitivity list, as its a clocked process, and clkDiv is being used AFTER the clock edge
Kr
avi
https://www.vlsiip.com
 

Iouri

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Sensitivity list

Also sensitivity list is for simulation ONLY, real staff doesn't need it all, but it makes code more readable
 

mta97e

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Re: Sensitivity list

clkDiv shouldnt be in the sensitivity list.

Also sensitivity list is for simulation ONLY, real staff doesn't need it all, but it makes code more readable

I do not agree with it.
In this particular case, there is no harm by putting clkDiv in the sensitivity. But sensitivity list governs the output of the synthesis and it could leads to disastrous sitiuations if we dont define the sensitivity correctly.
 

avimit

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Re: Sensitivity list

Dear mta97e
May I let you know with all respect, that you have got it wrong on this occasion. Sensitivity list is for simulation ONLY as said by Iouri. Synthesis is not effected by it**
In this perticular example however, as I said earlier clkDiv is redundant as its a clocked process. Putting it there will ONLY make things confusing, and may make the reader suspicious, as Nikolai has become.
Kr,
Avi
https://www.vlsiip.com

**Excluding some exceptions.
 

mta97e

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Re: Sensitivity list

thanks for pointing my mistake...



I remember, during my University days(2002), we were taught that sensitivity list governs the synthesized circuit.

It doesnt seems to apply anymore now. Is it becasue the synthesis tools become smarter?
Or the text book was wrong?
mark Zwolinski ... digital system design with vhdl
 

swapnil_vlsi

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Re: Sensitivity list

sensitivity list is for simulation ONLY

But even if "clkDiv" wasnt included in the

sensitivity list, its wont make any

difference since there must be an event on

CLK first for the process to proceed....

By applying it there ,it makes code more

readable

Yes the tool is smarter now...
 

avimit

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Re: Sensitivity list

Dear mta97e,
1.
I remember, during my University days(2002), we were taught that sensitivity list governs the synthesized circuit
I dont think so. No good university can teach that, because sensitivity list have no effect on synthesis since ages. Well there are exceptions, such as verilog where an async reset is governed by the inclusion of signal causing async reset in sensitivity lists. Also verilog will only infer registers if you have included a posedge or negedge of 'clock' in sensitivity lists. Apart from that synthesis is NOT affected by sensitivity lists, and it has never been.
Have a look at the codes
https://www.vlsiip.com/vhdl/sen.vhd **
and
https://www.vlsiip.com/vhdl/nosen.vhd **
The later has no signals in its sensitivity list(of the process labelled comb_p), and yet it synthesises just exactly same as the former one which has signals in the sensitivity list of the process labelled comb_p
If you dont believe me, you may want to use any design compiler or synthesis tool version dated back to 1990s, and you will have exactly the same results in both the cases.

2. There isn't any book which can advice that synthesis is affected by sensitivity lists, leaving exceptions described above. Just think, syntheis is not a god created magic, its a human created algorithm. If you are asked to do a manual 'synthesis' of a RTL code, then how can you change the results, just be inclusion or non inslucion of signals in sensitivity lists? it would be just un-implementable. You will just try to extract boolean equations out of RTL code using the signal assignment statements, no matter what the sensitivity list is.

3. I have taken lectures from Mr Mark Zwolinski at university of southampton in 2002, he NEVER taught us, neither he mentioned in his book that sensitivity list affects synthesis, leaving the exceptions.

So my dear, i dont know where you have got this concept from.

** These code has some minor non-recommended style of coding. i.e they are not perfect.

Kr,
Avi
https://www.vlsiip.com
 

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