hi
i am writing code for mux in verilog using UDP.
compilation is ok.
when i do simulation then this gives error like that -
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/modeltech_6.5/examples/verilogpermitive.v(17): Internal error: ../../../src/vlog/vtree_inline.c(1587) (typeof(module) == MODULE)||(typeof(module) == PROGRAM_DECL) || (typeof(module) == VL_CONFIGURATION_DECL)
# Optimization failed
# Error loading design
suggest me sthing how this error will be remove.