which library package include in verilog simulation

[mohdiliyasmalik]

hi
as we write
library ieee;
use ieee.std_logic_1164.all;
in vhdl for including library.
what we write in verilog to include library...............
I am writing same but didnt work....
any one suggest me............

 

[sakthikumaran87]

Actually You dont need any such library declaration in verilog

 

[mohdiliyasmalik]

hi
i am writing code for mux in verilog using UDP.
compilation is ok.
when i do simulation then this gives error like that -
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/modeltech_6.5/examples/verilogpermitive.v(17): Internal error: ../../../src/vlog/vtree_inline.c(1587) (typeof(module) == MODULE)||(typeof(module) == PROGRAM_DECL) || (typeof(module) == VL_CONFIGURATION_DECL)
# Optimization failed
# Error loading design

suggest me sthing how this error will be remove.

 

[sakthikumaran87]

i think you have to use -novopt command while simulating your design. Ex: vsim -novopt test_bench_name &