Which language is more fittable in the design verification? someone recommend the E language, other praise the c language.
which is more merge the SoC flow?
whether there are the ohter?
Re: Which language is more fittable in the design verificati
Hi,
I vote for C++.
I agree that C++ is much more tedious, and require engineers that think software and understand hardware.
To explain my reason, I challenge another other languages can than reuse the testbench across asic design/software algo design (e.g. dsp)/laboratory debug/anthing you can think of in complete verification of a chip.
I think system verilog is better , system verilog is same simulate with verilog , the other vera or specman is co-simulation , and system verilog is event base simulate, vera specman is cycle base simulate. Now cadence supply system verilog too.
Verilog testbench is traditional one. But more directly.
SystemVerilog and PSL assertion can make Verification easy.
SystemC is used to model system level integration in architecture design stage.
For e lanuage, I do not know much, but it is powerful. But current ESUNG give lots of question to Cadence CTO about 'e'. So it is not a bright future.
i think :
vera and system verilog : cycle based simuation. All signals are driven and sampled according to the clock (interface clock in vera; clocking block in SV)