Which language is more fittable in the design verification?

[visualart]

Which language is more fittable in the design verification? someone recommend the E language, other praise the c language.
which is more merge the SoC flow?
whether there are the ohter?

3s

 

[vivek]

Re: Which language is more fittable in the design verificati

you do have other poerful languages like vera and the upcoming system verilog.

which is more merge the SoC flow?

if u mean flexibility like reuse, HVL like vera/system verilog/Specman are much better compared to C or verilog/VHDL

 

[Summer.Xia]

systemc and verilog

 

[gaonkc]

systemverilog ,vera,verilog

 

[leeenghan]

Re: Which language is more fittable in the design verificati

Hi,

I vote for C++.

I agree that C++ is much more tedious, and require engineers that think software and understand hardware.

To explain my reason, I challenge another other languages can than reuse the testbench across asic design/software algo design (e.g. dsp)/laboratory debug/anthing you can think of in complete verification of a chip.

Regards,
Eng Han
www.eda-utilities.

 

[xworld2008]

I think system verilog is better , system verilog is same simulate with verilog , the other vera or specman is co-simulation , and system verilog is event base simulate, vera specman is cycle base simulate. Now cadence supply system verilog too.

 

[zhustudio]

Verilog testbench is traditional one. But more directly.
SystemVerilog and PSL assertion can make Verification easy.
SystemC is used to model system level integration in architecture design stage.
For e lanuage, I do not know much, but it is powerful. But current ESUNG give lots of question to Cadence CTO about 'e'. So it is not a bright future.

 

[vivek]

Re: Which language is more fittable in the design verificati

system verilog is event base simulate, vera specman is cycle base simulate

i think :
vera and system verilog : cycle based simuation. All signals are driven and sampled according to the clock (interface clock in vera; clocking block in SV)

specman e : event based simulation

 

[mohdfaisal]

I create my verilog source code using Xilinx and I have a problem to use it in Synopsys. Can anybody give me a suggestion to solve my problem