Here is the definitions of "PLL period jitter" and "PLL cycle-to-cycle jitter" bellow.
Which jitter should be considered as "clock uncertainty" in STA (just for setup check, no affect to hold check)?
Period Jitter (A), (JEDEC Definition - JESD65)
The edge deviation to the ideal FOUT when measuring the rising edge of FOUT after
(n+N)-th cycle by using the rising edge of FOUT at n-th cycle as the trigger point, where N=1. FOUT is PLL's output.(figure 1)
Cycle-to-Cycle Jitter (JEDEC Definition - JESD65)
The cycle time variation between adjacent cycles over a random sample of adjacent clock cycle pairs.(figure 2)