whether latency can change or not

[sun_ray]

Suppose we are doing retiming while doing synthesis. Can this retiming affect the latency? Sometimes customer wants the latency not to be changed.

 

[FvM]

Latency is usually referring to full clock cycles, not delay/fine timing. Retiming should never change the latency in terms of clock cycles.

 

[sun_ray]

Do we need any extra license for roing retime while doing retime doring synthesis by Cadence RTL Compiler? What about Design Compiler? Does Design Compiler require any extra license for doing retime?

 

[jeet_asic]

Does retiming means "borrowing time" .. ? i.e if one of the path has +ve slack n any other path has -ve slack , so tool borrows timing from +ve slack time . can this happen?

 

[FvM]

Does retiming means "borrowing time" .. ?

Sounds like a visual explanation to me.

 

[raju3295]

it not time borrowing, actually, the combo itself moved to next or before in the pipeline, or we can say as repositioning of the flops.

 

[jeet_asic]

it not time borrowing, actually, the combo itself moved to next or before in the pipeline, or we can say as repositioning of the flops.

Thanks. One more doubt ... won't re-positioning affect circuit working ?

 

[englishdogg]

@sun_ray, @jeet_asic,

Retiming is executed without changing the input-output latency; more or less a technique for improving performance of seq circuits by repositioning flops to benefit in cycle time or area. Pipelining is also a subset of retiming where sufficient stages of registers are added to the design.

To my knowledge yes, a special license is required for this feature within synthesis tools.

Hope this helps.

 

[jeet_asic]

thanks. on what factors does borrowing time depend. sometimes after borrowing maximum borrowing time also slack is violated (primetime tool), so on what factor will it depend.

@sun_ray, @jeet_asic,

Retiming is executed without changing the input-output latency; more or less a technique for improving performance of seq circuits by repositioning flops to benefit in cycle time or area. Pipelining is also a subset of retiming where sufficient stages of registers are added to the design.

To my knowledge yes, a special license is required for this feature within synthesis tools.

Hope this helps.

 

[sun_ray]

@sun_ray, @jeet_asic,

Retiming is executed without changing the input-output latency; more or less a technique for improving performance of seq circuits by repositioning flops to benefit in cycle time or area. Pipelining is also a subset of retiming where sufficient stages of registers are added to the design.

englishdogg or FVM

I think retime is only done for improving performance and not for benefit of cycle time and area as stated by you. Please correct me if I am wrong. Does the definition of retime states that it will not change the latency? If I am not wrong the definition of retime only states that the retime is used to re position the flip flops for improving timing. Please correct me again if I am wrong.

To my knowledge yes, a special license is required for this feature within synthesis tools.

Can you please let me know the name of the special license for retime for Cadence and also for Synopsys tool suit.

 

[englishdogg]

@jeet_asic

Your correct retime does have some dependency - for retiming to successfully occur there has to be a positive slack on the either side for the time to be borrowed.

@sun_ray,

yes - retime should not change the latency or the combinational logic. To my knowledge retiming can be executed for area gain as well.
I believe for Cadence there is a GXL license that is required, pls note that the licensing keeps on changing by the vendors depending on the versions; you may want to confirm with the vendor.

Uploading a pic to see if this make sit clear...