Hi, I'm a new member here.
I think your question should be solved with MMMC, multi-mode multi-corner.
if in test mode, the tool sees the hold violation, it will automatically take care of it.
owen_li said:
thank you for your response! vlsichipdesigner
I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?
Thanks!
Added after 8 minutes:
thank you for your response! vlsichipdesigner
I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?
Thanks!