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where to insert the lockup latches

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owen_li

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As we know, we should insert lockup latches between cross clock domains to avoid hold violation.
My question is: Should we insert the lockup latch on the shift path or capture path.
The shift path means from Previous register output to next register scan input
The capture path means from Previois register output to next register D input.

My understanding is: these two pathes both have the potential to fail the hold check
because of the clock skew. Should we insert the lockup latches on both paths?

Thank yoU!
 

vlsichipdesigner

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hi,

my 2 cents,

We apply the lockup latches, only to scan-shift path to address hold violations.

scan -capture,would get addressed in functional mode and the probability of hold violations is less.

myprayers,
chip design made easy
https://www.vlsichipdesign.com
 

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owen_li

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thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!

Added after 8 minutes:

thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!
 

    V

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jaydip

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see, if functional path is valid, why will anyone define it as a false path?? and if it functional path is valid, hold and setup violation will anyhow be taken care .. is it not?
 

raju3295

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hi jaydip,
Its a false path in the functional mode but valid path in the testmode.
 

jaydip

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if these paths are clock domain crossing paths (defined as false path in functional mode), lock-up latch takes core of hold violation in test mode and synchronizers takes care of hold violations in functional mode .. what are others path which are false in functional mode and valid in test mode? I hope make sense ...
 

h.edaboard

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Hi, I'm a new member here.
I think your question should be solved with MMMC, multi-mode multi-corner.
if in test mode, the tool sees the hold violation, it will automatically take care of it.

owen_li said:
thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!

Added after 8 minutes:

thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!
 

arunkumar446

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Hi jaydip,

can you elaborate on synchronizers and can you refer me to any papers and docs related to synchronizers and lockup latches.


Thanks in advance.
 

raju3295

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i think multicycle paths in the funcctional paths are false path in testmode.
arunkumar446 said:
Hi jaydip,

can you elaborate on synchronizers and can you refer me to any papers and docs related to synchronizers and lockup latches.


Thanks in advance.

synchronizes are nothing but like shift registers kept between the clock domain crossing paths , clocked by capturing clock
 

arunkumar446

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raju3295 said:
i think multicycle paths in the funcctional paths are false path in testmode.
arunkumar446 said:
Hi jaydip,

can you elaborate on synchronizers and can you refer me to any papers and docs related to synchronizers and lockup latches.


Thanks in advance.

synchronizes are nothing but like shift registers kept between the clock domain crossing paths , clocked by capturing clock


Hi, can you give me an example or refer me to some doc which has an example in it.
thanks in advance.
 

raju3295

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sorry i did't get for what ur asking reference
 

pete_lu

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h.edaboard said:
Hi, I'm a new member here.
I think your question should be solved with MMMC, multi-mode multi-corner.
if in test mode, the tool sees the hold violation, it will automatically take care of it.

owen_li said:
thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!

Added after 8 minutes:

thank you for your response! vlsichipdesigner

I am still curious of this issue.
In my opinion, we will usually set false path between clock domains, except the synchronous clock domains.
So the functional timing mode run will not care these hold violation between clock domains. But when in the test timing mode, these hold violations will come out!
How do you handle this situation ?

Thanks!
MMMC is the right answer, we don't need to insert lockup cells in scan-capture path since hold violation in scan-capture mode will be fixed in scan-capture mode analysis!
And scan cts will be implemented after function cts, so we don't need to take care of clock skew in scan capture mode.
 

rakko

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The sole purpose of lockup latch is to allow reliable shifting in scan shift mode and therefore is not necessary to put them in functional paths. When we de-assert scan+enable, the chip temporarily comes out of the scan and enters functional mode. If the functional mode does not have hold violations, then, you shouldn't see any in test mode either. I think someone mentioned some of this earlier.
 

owen_li

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Thanks for your response.

But I think there are indeed some pathes valid in test mode, and invalid in functional mode.
I mean these pathes' timing check will be don't cared, like crossing clock domains.
But when running in test mode, the output of previois clock domain should be captured by the latter clock domain. So the path is valid in test mode.

How can you guarantee the path is absent of hold violation ?
 

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