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The most important one is gate connection. For NMOS you connect it to GND and PMOS to VDD. Thats mean your transistor is always off. No functional purpose.
What is your verification tool? That warning was flagged because in the DRC rule they just want to confirm our connection as normally VCC is connected to source of PMOS. This shouldn't be a problem as long as you understand the warning. You always can check the rule deck for reference.
For me your problem comes from ESD problem, problably you are working into a I/O team.
So normaly you don't have the right to connect a Gate directly to VDD or VSS without ESD protection.
But in your case you don't care about this problem , I guess , but you need to check it.
May you tell me if it's right ,you are involve in I/O design , please ?
The most important one is gate connection. For NMOS you connect it to GND and PMOS to VDD. Thats mean your transistor is always off. No functional purpose.
Can we connect the dummy transistor gate to the gate of the function transitors, while connect the source and drain of the dummy transistor to GND for NMOS dummy and VDD for PMOS dummy?
I think this will increase the capacitor of the function transistor gate terminal, is it acceptable?
The most important one is gate connection. For NMOS you connect it to GND and PMOS to VDD. Thats mean your transistor is always off. No functional purpose.
Can we connect the dummy transistor gate to the gate of the function transitors, while connect the source and drain of the dummy transistor to GND for NMOS dummy and VDD for PMOS dummy?
I think this will increase the capacitor of the function transistor gate terminal, is it acceptable?
Yes , this will increase the capacitor of the function transistor gate terminal, it is not acceptable.
We usually connect the 4 terminal of dummy NMOS to VSS and dummy PMOS to VDD. If the tools report warning when doing ERC, you can set some options of the tool to ignore it .
yes, it's used for current mirror.
Sometimes we're required to make them as optional transistors as well for topmost metal FIB. So it's not easy to connect all the 4 terminals to VDD/VSS all with the topmost metal. In this case, the easiest way are to connet only one terminal (gate or drain) of the dummy transistor to VDD/VSS with topmost metal, while keep the other terminals connecting to the same terminal of the function transistors. But I'm not sure if it's OK or not.
If it's OK, which way is better, to connect the gate to VDD/VSS or to connect the drain to VDD/VSS?
In this case, the easiest way are to connet only one terminal (gate or drain) of the dummy transistor to VDD/VSS with topmost metal, while keep the other terminals connecting to the same terminal of the function transistors. But I'm not sure if it's OK or not.
If it's OK, which way is better, to connect the gate to VDD/VSS or to connect the drain to VDD/VSS?
I think it is not reasonable to connect the other terminals to the function transistors and connect the gate of dummy transisitor to VDD/VSS or drain to VDD/VSS. that will disturb the function of the function transistors.
yeah, dummy should not be connected to the functional devices because it disturbs the ac signals flowing through it.
PMOS should be connected to VDD and NMOS to VSS; i mean all of its terminals.
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