Where is the use of 'BUSY' transfer type in AHB?

[ghansham.eln]

ahb busy

In AHB Lite or even in Full AHB, Specification tells that BUSY transfer type indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately.
I have seen no design yet which has used the the 'BUSY' transfer type in Master or in Slave Design. Is that just provided as specification or really is used anywhere?
Can anybody explain with example where it is used?

 

[Riveywood]

BUSY is certainly used by some AHB designs, although many masters do not require it. If you are designing a general purpose slave that can be used in any system, you should make it support BUSY (if it is burst capable). Otherwise, check with the designer of the master to see whether it uses BUSY.

A very simple example - consider a CPU which is being clocked slower than the AHB system. It can't use the data as quickly as the bus system is providing it, so it needs to insert BUSY between beats of a burst. If the CPU was the only thing in the system, it would probably make no sense for it to be faster than AHB speed. But if there are multiple masters and the CPU is in a low power mode where it is being clocked slowly while waiting for an interrupt or something like that, it can happen.

Plenty of the newer ARM CPUs use BUSY - even when being clocked much faster than the bus.

I wrote a little bit about the restrictions on BUSY here:
**broken link removed**