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PLL are always implemented in FPGA/ASIC as hard-cores. There is no need to describe it on VHDL to use in your design and you can confige on-chip PLLs with EDA tools. Or you just want to have a model of PLL to perform a modeling of system?allouche said:Hi,
Does anyone know where i can get a PLL core(in VHDL), for a frequency multiplier application ?
Thanks
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