jdhar
Full Member level 5
Hi there,
I have a question about when to change signals. It seems like if I use a simple register that is synchronous, the output of the register will change on the rising edge of the clock, correct (I am talking about RTL in an FPGA)? However, if i am interfacing with external components, this seems like it would violate setup/hold times, and I should be transitioning on the falling edge of the clock instead. For example, a chip select line for an SDRAM. If I have it change the same time as a rising edge, that will surely be asking for trouble since different delays of the signals reachign the RAM will cause a problem. So, is it common to use two clocks, one 90 degrees phase-shifted from another? How is this typically done?
Thank you, Jai.
I have a question about when to change signals. It seems like if I use a simple register that is synchronous, the output of the register will change on the rising edge of the clock, correct (I am talking about RTL in an FPGA)? However, if i am interfacing with external components, this seems like it would violate setup/hold times, and I should be transitioning on the falling edge of the clock instead. For example, a chip select line for an SDRAM. If I have it change the same time as a rising edge, that will surely be asking for trouble since different delays of the signals reachign the RAM will cause a problem. So, is it common to use two clocks, one 90 degrees phase-shifted from another? How is this typically done?
Thank you, Jai.