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When should I do signal transition?

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jdhar

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Hi there,

I have a question about when to change signals. It seems like if I use a simple register that is synchronous, the output of the register will change on the rising edge of the clock, correct (I am talking about RTL in an FPGA)? However, if i am interfacing with external components, this seems like it would violate setup/hold times, and I should be transitioning on the falling edge of the clock instead. For example, a chip select line for an SDRAM. If I have it change the same time as a rising edge, that will surely be asking for trouble since different delays of the signals reachign the RAM will cause a problem. So, is it common to use two clocks, one 90 degrees phase-shifted from another? How is this typically done?

Thank you, Jai.
 

Re: Signal transitions

Better than 90 degrees, think about a 180 degrees shift. That would be your clock inverted.

To generate control signals, you must asure that they are stable when the controled device sample them. So if the controled devibe samples signals at rising edge, it's a good practice to generate them at falling edge.
 

Signal transitions

woops, I meant 180. However, my question is that is this what is commonly done with FPGA's? Or are there other methods used ... if I were to do this, I take it that I would have a regular PLL output going to my logic block, and then a 180 phase shift going to my device outside the FPGA?
 

Signal transitions

If you interface with external components always register the inputs you take and the outputs you produce, so they are stable.
 

Re: Signal transitions

maybe you guys can help me out with this.

My design has a 16 bits registered output. The output from the FPGA (16 bits bus) is very 'glitchy'. I believe that I need to set some delay matching constraints so that the 16-bits are toggling at the same time to remove the glitches. All I know is that I can group these 16 bits and then set the offset out constraints. I tried this, but the output is still very "glitchy". Does anyone know what other timing constraints could be applied to solve this problem?

thank you.
 

Signal transitions

arm7tdmi, what do you mean by "glitchy"? Your registered outputs should transition only on the clock edges, unless you have some awful hardware problem.

For best results, put your register in the I/O flip-flops. That minimizes flipflop-to-pad routing delays, so all your output bits will transition almost simultaneously.
 

Re: Signal transitions

for 90 degree phase shift, we usually use DLL technology,

the DLL is made of four stage delay cells, when the DLL is into lock,

the DLL's output clock will phase align with the input clock,

then each stage will delay 90 degree, we can chose first stage's

output for 90 degree phase shifted signal.


best regards





jdhar said:
Hi there,

I have a question about when to change signals. It seems like if I use a simple register that is synchronous, the output of the register will change on the rising edge of the clock, correct (I am talking about RTL in an FPGA)? However, if i am interfacing with external components, this seems like it would violate setup/hold times, and I should be transitioning on the falling edge of the clock instead. For example, a chip select line for an SDRAM. If I have it change the same time as a rising edge, that will surely be asking for trouble since different delays of the signals reachign the RAM will cause a problem. So, is it common to use two clocks, one 90 degrees phase-shifted from another? How is this typically done?

Thank you, Jai.
 

Re: Signal transitions

The company I work for uses DCM to provide the phase shift for QDR and DDR memories.
 

Signal transitions

How about connecting a simple inverter and feeding the output to the external clock, while clocking inside the FPGA un-inverted? Is this recommended?
 

Re: Signal transitions

echo47,

how do I place the register in the IO?
In map option, i have 'enabled' the option for "Pack I/O Registers/Latches into IOBs". This does not seem to solve the problem of getting all the bits to be transitioned at the same time.

Please help. Thank you.
 

Re: Signal transitions

jdhar said:
How about connecting a simple inverter and feeding the output to the external clock, while clocking inside the FPGA un-inverted? Is this recommended?

That seem to work. Just tried it recently running at 125 MHz.
 

Re: Signal transitions

I haven't followed this thread for a couple weeks. Is your problem solved?

If the IOB register packing command didn't help, are you sure it really accepted the command? You can check the mapper report, or use FPGA Editor to examine the IOBs in the routed chip.

In my verilog, I use //synthesis attribute IOB registername "TRUE"

The IOB register isn't as flexible as a slice register. In some designs, it can't put the register into an IOB, so it will ignore your request. In that case, study the IOB architecture, and try rearranging your design.
 

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