I am into FPGA, Can u please say where the STA comes into the picture while implementing the design on FPGA, and what all the things i have to check for STA
STA comes into picture when you you to analyze the timing delays, wire load models, see the net delays, faults, see if there is Set up/ Hold violation etc.
STA comes after you have done logic synthesis and also after place&route.
You can use STA when you have a gate-level netlist.
Use STA to check for setup, hold and pulse width. Basically use it to check if your design meets its timing constraints.