module div (
SCAN_EN_SCLK , /*Scan Enable*/
SCAN_IN_SCLK , /*Scan Input*/
SCAN_OUT_SCLK, /*Scan output */
rb_por_cr , /*Asynchronous reset*/
SCLK , /*Divider Clock*/
divisor , /*divisor*/
we , /*write enable - initiate dividing*/
result /*division result*/
);
/*Port direction and types*/
output [7:0] result ;
reg [7:0] result ;
input [7:0] divisor ;
wire [7:0] divisor;
input SCLK ;
wire SCLK ;
input we ;
wire we;
input rb_por_cr;
input SCAN_EN_SCLK;
input SCAN_IN_SCLK;
output SCAN_OUT_SCLK;
/*Internal signal declaration*/
reg [8:0] cur_divident;
reg [6:0] cur_divisor;
reg [2:0] bit_count;
integer i;
reg [2:0] max;
/*Functional description*/
/*Create logic finding MSB 1*/
always@(divisor)
begin
max=0;
for(i=7;i>0;i=i-1)
if(divisor[i]==1'b1 & i>=max)
max=i;
end
wire [7:0] tmp_div=divisor<<(7-max);
/*Division*/
always@(negedge rb_por_cr or posedge SCLK)
if(!rb_por_cr)
begin
cur_divident<=8'd0;
cur_divisor<=8'd0;
bit_count<=3'd0;
result<=7'd0;
end
else if(we)
begin
cur_divident<=9'd255-tmp_div;
cur_divisor<=tmp_div>>1;
bit_count<=8-max;
if (max==0)
result<=8'hFF;
else
result<=7'd0;
end
else if (bit_count>3'b000)
begin
if (cur_divident[8]==1'b0)
begin
cur_divident <= cur_divident-cur_divisor;
`ifdef debug_modeling
assert (bit_count!=3'b000) result[bit_count-1'b1]<=1'b1; else $fatal(0,"Division error selected out of range");
`else
result[bit_count-1'b1]<=1'b1;
`endif
end
else
begin
`ifdef debug_modeling
assert (bit_count!=3'b000) result[bit_count-1'b1]<=1'b0; else $fatal(0,"Division error selected out of range");
`else
result[bit_count-1'b1]<=1'b0;
`endif
cur_divident <= cur_divident+cur_divisor;
end
bit_count<=bit_count-1;
cur_divisor<= cur_divisor>>1;
end
endmodule