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Whats the unit delay used in timing when simulating netlist

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RTL2GDSII

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Unit delay question !

When simulating the netlist generated by systhesis tool, there is a unit delay used in timing. What's this unit delay ? Why not just use the timing generated by wire load model ?
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gnomix

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I don't know if I have understand correctly but the unit delay during the timing simulation can be used to verify the functional model of the netlist, all cell have a unit delay and the "path delay" don't derive of the wire load and the delay cells.
 

Ohh

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The unit delay model is usually used for functional simulation. For example, all gates are assumed to have the same delay value and all wire delays are assumed to be zero. This is useful for functional simulation. For timing simulation one usually uses other delay models for both gate delays and wire delays.
 

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