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Fpga speed grade is a maximum frequency at which the flops in fpga can run. Example, a altera apex -1 runs faster (~ 250 MHz as I remember) than a altera apex -2 or -3. Of course, a device run faster which is more expensive.
In Xilinx devices there is no connection between these speed grade numbers and any of timing properties. The only you could get from these numbers is that for old FPGAs like XC4000 and CPLD the smaller number means faster device. For last FPGAs like all Virtex and Spartan2 the bigger number correspond to the faster device of the same series. For example, Virtex-8 is faster than Virtex-6, but slower than Virtex2-6! In others words you have to check timing after PaR for different devices to select the one that correspond to your needs.
Max is right, it is a quality index used by the manufacturers. Usually the chips on the perifery of the silicon wafer will not be of that good quality compared to that at the centre. This is one of the factors that decides on the swpeed grade. Also I have come to know about this but I am not sure, speed grade reflects the spacing clb's,slices,luts etc thereby reducing or increasing the routing delay.