Handling of DQS timing is the most critical design task in DDR design. one must use very critical time adjustments using DLL for matching DQS timing & phase requirement.
And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from Altera. It supports DDR interface and costs about 30$.
And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from @ltera. It supports DDR interface and costs about 30$.
Because what funster said is: "Do I need some analog circuits such as DLL?" , I think this is an asic design, if he use a fpga, he can use the DCM in fpga, and don't need any analog circuits. However, I agree with you in a fpga design, if the project allowed, using fpga will be the best way and implement easily, there is a demo on xilinx's website.