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# What's the most important in designing DDR SDRAM controller?

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#### funster

##### Full Member level 4
recently, I need to design a DDR 266 controller for out project,

I want to know what's the most important in designing DDR SDRAM controller,

Do I need some analog circuits such as DLL?

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2005 12 23

#### alex_fn

##### Junior Member level 2
Re: DDR controller

to Design a DDR controller what type of fpga you used?
or you can survy the vendor 's site for detail,

As i know,achieveing DDR timing might be with some diffculties

#### maksya

##### Full Member level 3
Re: DDR controller

funster said:
Do I need some analog circuits such as DLL?

You have to phase-shift the data strobe signal (DQS). Using DLL is the best way to implement such delay. Most of FPGA have on-chip DLL block.

#### cfriend

##### Full Member level 1
DDR controller

I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

#### maksya

##### Full Member level 3
Re: DDR controller

cfriend said:
I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

A lot of FPGA solves this problem. Simply find chips with support of SSTL-II IO standard (used in DDR SDRAM).

##### Full Member level 4
Re: DDR controller

Hi funster,

If it is possible you can try Den@lis Ip FOR DDR, it has lesser risk than you design a new one.

#### silencer3

DDR controller

Handling of DQS timing is the most critical design task in DDR design. one must use very critical time adjustments using DLL for matching DQS timing & phase requirement.

#### cfriend

##### Full Member level 1
Re: DDR controller

maksya said:
cfriend said:
I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

A lot of FPGA solves this problem. Simply find chips with support of SSTL-II IO standard (used in DDR SDRAM).

what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money.

#### maksya

##### Full Member level 3
Re: DDR controller

cfriend said:
what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money.

And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from Altera. It supports DDR interface and costs about 30$. #### cfriend ##### Full Member level 1 Re: DDR controller maksya said: cfriend said: what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money. And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from @ltera. It supports DDR interface and costs about 30$.

Because what funster said is: "Do I need some analog circuits such as DLL?" , I think this is an asic design, if he use a fpga, he can use the DCM in fpga, and don't need any analog circuits. However, I agree with you in a fpga design, if the project allowed, using fpga will be the best way and implement easily, there is a demo on xilinx's website.

#### WILLIAM.YAO

##### Newbie level 4
DDR controller

i think altera starix/ii fpga family are very good, cause they have ddr ioe, i have run ddr 266 on it.

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