What's the most important in designing DDR SDRAM controller?

[funster]

recently, I need to design a DDR 266 controller for out project,

I want to know what's the most important in designing DDR SDRAM controller,

Do I need some analog circuits such as DLL?

BEST REAGRDS

2005 12 23

 

[alex_fn]

Re: DDR controller

to Design a DDR controller what type of fpga you used?
or you can survy the vendor 's site for detail,

As i know,achieveing DDR timing might be with some diffculties

 

[maksya]

Re: DDR controller

Do I need some analog circuits such as DLL?

You have to phase-shift the data strobe signal (DQS). Using DLL is the best way to implement such delay. Most of FPGA have on-chip DLL block.

 

[cfriend]

DDR controller

I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

 

[maksya]

Re: DDR controller

I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

A lot of FPGA solves this problem. Simply find chips with support of SSTL-II IO standard (used in DDR SDRAM).

 

[wadaye]

Re: DDR controller

Hi funster,

If it is possible you can try Den@lis Ip FOR DDR, it has lesser risk than you design a new one.

 

[silencer3]

DDR controller

Handling of DQS timing is the most critical design task in DDR design. one must use very critical time adjustments using DLL for matching DQS timing & phase requirement.

 

[cfriend]

Re: DDR controller

I think the IOcell is also very important, you must use a high speed IO, so i think the control logic is simple, but the IO cell will cost many

A lot of FPGA solves this problem. Simply find chips with support of SSTL-II IO standard (used in DDR SDRAM).

what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money.

 

[maksya]

Re: DDR controller

what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money.

And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from Altera. It supports DDR interface and costs about 30$.

 

[cfriend]

Re: DDR controller

what I talk about is an ASIC design, not in FPGA, the SSTL-II IO will cost a lot of your money.

And why do you think that using ASIC is critical for funster? Talking about FPGA I suggest that it is the most cheaper choise. For example, Cyclone from @ltera. It supports DDR interface and costs about 30$.

Because what funster said is: "Do I need some analog circuits such as DLL?" , I think this is an asic design, if he use a fpga, he can use the DCM in fpga, and don't need any analog circuits. However, I agree with you in a fpga design, if the project allowed, using fpga will be the best way and implement easily, there is a demo on xilinx's website.

 

[WILLIAM.YAO]

DDR controller

i think altera starix/ii fpga family are very good, cause they have ddr ioe, i have run ddr 266 on it.