Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In ASIC back end the we do floor plan, placement, layout and then simulations for checking the correct functionality and timing, parasitics etc.
at last it is delievered to fab for manufacturing.
in simple terms u can say after synthesis everything comes in Backend
thanks a lot
thank you very much
because i am doing pcb layout and routing
i want to move from pcb to asic backend
i dont know any thing about asic back end
any body have pdfs to learnd basics of asic backend
please send it
thanks in advance
Hi
Let me tell about the Backend work that we do in my company..
The work would be stringent and tough ...Unlike front end, we get only 2months(might be 3 or 4 also ) to design and verify the floorplanning, routing etc..It will be challenging ,,but u will like it once u get going .
All the best dude and welcome to Back End Design Engineers...
Thanks
in simple way asic backend....we implement the logic(in real hardwar...i.e chip) developed by front end engineers(they use verilog,VHDL....)....during that process...backend(physical design engg) has to follow...certain flows ...depending on the applications...and many other factors.....hope this helps.....
ASIC Back End Design involves the conversion of synthesis netlist in to geometrical information in the shape of rectangles called layouts. Usually Back End design process have steps like partitioning, floorplanning,placements,routing,DRC,LVS,parasitic extraction and generation of GDS-II which is required by foundary for chip fabrication. Before sending the GDS-II for mask preparation the design should be verified using sign-off tools to confirm that there is no violation of any design rules, power and signal Integrity. it is considered to be a very difficult but interesting domain in VLSI design. High end tools are required for this purpose.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.