hi zeeshanzia84
the input signal that i give is analog,so i don't think this circuit is about ECL/CML
ya! lladnar23
i simulate the circuit without the Q10,the voltage drop the gate of MP19 is about 0.23v when Q9 is in active region ,and with Q10 the voltage is about 3.1v, that's mean a diode clamp? can you remind the detail of a diode clamp in a comparator?
now, if Q10 is to limit the voltage, the current through it is not needed to be considered because it's too little.right?