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choonlle said:what is the different between case1 and case 2?
case 1:
always (a)
begin
b=a;
end
case2:
assign b=a;
choonlle said:that's means , in always statement, b must be register ?! do you think possible b is wire in always statement ?
Thanks!
choonlle said:that's means , in always statement, b must be register ?! do you think possible b is wire in always statement ?
Thanks!