What's the best SRAM configuration? (4T, 5T, 6T, etc)

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ajhunt18

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What's the best SRAM configuration? (4T, 5T, 6T, etc). I am designing an SRAM with low power and low leakage in digital implementation using Verilog coding (VCS simulation). Also, what's the best technique I can use to minimize the leakage?

Thank You!
 

what structure of 5T like?
4T just derived from 6T(2T as resistor in 4T).
 

I am actually designing in digital implementation. I will use latches instead of nmos or pmos transistors. I'll be using cross-coupled inverter.
 

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