many time i saw back end engineer use SPEF for timing analyse and so on.
but what's SPEF and what information does it contains?
would u send some materals about it?
thank u
Hi,
SPEF stands for Standard Parasitic Exchange Format. It contains the parasitics extracted from the layout. Backend engineers needs these information to do post layout STA. You may search the web for the detailed information about this format.
SPEF Standard-parasitic extended format. Part of Open Verilog International's delay-calculation-system (DCS) standard. Based primarily on SPF, SPEF has extended capability and a smaller format. Although many EDA back-end tools support DSPF and RSPF, few EDA tools support SPEF at this time.
i saw that SPEF mean standard physical exchange format.
can anybody describe the content of SPEF?
or give me a simple exmple for understanding.
thank u
Please cehck the details of SPEF and their syntax at the following link...
h**p://vlsi-expert.blogspot.com/2010/08/difference-between-parasitic-data.html
spef is extracted after routing in pnr stage. This helps in accurate calculation of IRDROP analysis and other analysis after routing. This file contains the R and C paramaters depending on the placement of our tile/block and the routing among the placed cells..
Please cehck the details of SPEF and their syntax at the following link...
h**p://vlsi-expert.blogspot.com/2010/08/difference-between-parasitic-data.html
spef is extracted after routing in pnr stage. This helps in accurate calculation of IRDROP analysis and other analysis after routing. This file contains the R and C paramaters depending on the placement of our tile/block and the routing among the placed cells..