what's SPEF and what information does it contains?

[bendrift]

spef d_net

many time i saw back end engineer use SPEF for timing analyse and so on.
but what's SPEF and what information does it contains?
would u send some materals about it?
thank u

 

[bendrift]

standard parasitic exchange format

would someone help me?

 

[ceyjey]

spf spef

Hi,
SPEF stands for Standard Parasitic Exchange Format. It contains the parasitics extracted from the layout. Backend engineers needs these information to do post layout STA. You may search the web for the detailed information about this format.

ceyjey

 

[icon]

spef format d_net

SPEF Standard-parasitic extended format. Part of Open Verilog International's delay-calculation-system (DCS) standard. Based primarily on SPF, SPEF has extended capability and a smaller format. Although many EDA back-end tools support DSPF and RSPF, few EDA tools support SPEF at this time.

 

[bendrift]

spef documentation

i saw that SPEF mean standard physical exchange format.
can anybody describe the content of SPEF?
or give me a simple exmple for understanding.
thank u

 

[utmseng]

what does spf mean in eda

Hi,

Here is the SPEF file example I copied from somewhere.

SPEF
*SPEF “IEEE 1481-1998”
*DESIGN “top”
*DATE “Wed May 17 19:50:14 2000”
*VENDOR “Synopsys”
*PROGRAM “Star-RCXT”
*VERSION “2003.2.0.0”
*DESIGN_FLOW “PIN_CAP NONE” “NAME_SCOPE LOCAL”
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 FF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*5 net1
*10 insta/net2
*14 U1
*16 insta/U1
*17 insta/U2
*PORTS
*5 I *C 3.6 0
*D_NET *5 1.02e+00
*CONN
*P *5 I *C 3.6 0
*I *14:I I *C 6.76 8.94 *L 4 *D inv
*CAP
1 *5 0.60481
2 *14:I 0.413795
*RES
1 *5 *14:I 29.8492
*END
*D_NET *10 4.58e-01
*CONN
*I *16:ZN O *C 9.12 21.84
*I *17:I I *C 6.34 20.94 *L 4 *D inv
*CAP
1 *16:ZN 0.271701
2 *17:I 0.186
*RES
1 *16:ZN *17:I 16.8989
*END

For the explanation of the SPEF file, you can refer to a documentation posted by usernam
h**p://

Have fun!

 

[tarkyss]

spef ieee 1481-1998

RC parameter

 

[sam31]

star-rcxt spef d_net

SPEF : parasistic parameter R (ohm) & C (farad) for RC timing modeling

Used after layout to back-annotate timing for STA & simulation

 

[birdy123]

Hi GUys,

Please cehck the details of SPEF and their syntax at the following link...
h**p://vlsi-expert.blogspot.com/2010/08/difference-between-parasitic-data.html

and

h**p://vlsi-expert.blogspot.com/2010/08/how-to-read-spef.html

 

[hari151087]

spef is extracted after routing in pnr stage. This helps in accurate calculation of IRDROP analysis and other analysis after routing. This file contains the R and C paramaters depending on the placement of our tile/block and the routing among the placed cells..

 

[MRAMA]

Hi GUys,

Please cehck the details of SPEF and their syntax at the following link...
h**p://vlsi-expert.blogspot.com/2010/08/difference-between-parasitic-data.html

and

h**p://vlsi-expert.blogspot.com/2010/08/how-to-read-spef.html

spef is extracted after routing in pnr stage. This helps in accurate calculation of IRDROP analysis and other analysis after routing. This file contains the R and C paramaters depending on the placement of our tile/block and the routing among the placed cells..

Please see the date of the thread.....

its 05 year.. and i think they might have got solution for it by now....

DONT REOPEN OLD THREADS AS THEY MIGHT HAVE DIED LONG BACK AND NEW THREADS MAY BE OVERRIDDEN