what's error the following source code?

[lzh08]

module LED_flush(rst,clk,led3,led2,led1,led0);
input clk,rst;
output led3,led2,led1,led0;
reg led3,led2,led1,led0;

reg[21:0] Mega_cnt;

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
Mega_cnt<=0;
end
else
begin
Mega_cnt<=Mega_cnt+1;
led3 <= 1;
led2 <= 0;
led1 <= 1;
led0 <= 0;
end
end

//assign led = Mega_cnt[21];
always @(posedge clk)
begin
if(Mega_cnt[21])
begin
led3 <= 1;
led2 <= 0;
led1 <= 1;
led0 <= 0;
end
end
endmodule

 

[echo47]

What do you expect it to do, and what is it doing instead?

 

[Epegic]

Verilog don't allow assign same register in more than one always statement.
You had LED0-4 assigned in both always statement!

 

[yousuf]

Hi,

To know the "error" in your code, you should tell us what it is supposed to do.

From the code I could imagine that you are trying to flash LEDs alternately, i.e. led0 and led2 turn on together then led1 and led3 and so on. Is that the case?

Again judging from the code, it seems that the large counter is there to divide the master clock by 4 mega cycles since you are trying to use it's MSB i.e bit 21. It is probably there to divide the very fast master clock and to bring it into the range where the human eyes could see the leds flashing. Right?

Anyways, as far as Verilog goes, there is no "error" in the code, except that you are not alternating the leds, i.e. you are turning on led1 and led3 both times instead of toggling them.

The synthesizer, however, will complain big time! The code is not synthesizable because you have used logic elements in multiple blocks e.g. the led regs. You should re-write the code such that each logic element (the led regs and the mega cycle counter) appear in only one block.

Consider the following:


module LED_flush(rst,clk,led3,led2,led1,led0);
input clk,rst;
output led3,led2,led1,led0;
// reg led3,led2,led1,led0; //probably no need for regs, wires will do for flashing

reg[21:0] Mega_cnt;

always @ (posedge clk or negedge rst)
if (!rst) Mega_cnt <= 0;
else Mega_cnt <= Mega_cnt + 1;

assign led3 = Mega_cnt[21];
assign led1 = Mega_cnt[21];

assign led2 = !Mega_cnt[21];
assign led0 = !Mega_cnt[21];

endmodule


Now the behaviour for each logic element is in one Verilog block only:

Mega_cnt : only one always block
led0 : only one assign block
led1 : only one assign block
led2 : only one assign block
led3 : only one assign block

Completely synthesizable, I just hope it does what you were looking for



Later.