Matrix_YL
Advanced Member level 4
Hi all
I have twenty pairs of LVDS (as input) to connect with PADs of spartan2e and want to output LVTTL with left PADS .
I don't understand about Vcco clearly
I find this in xilinx datasheet about spartan2e (In the TQ144 and PQ208 packages, the eight banks have VCCO connected together.)whether that's means if I select LVDS as IOSTANDARD ,the PADs no matter input or output are all been LDVS ,that is due to Vcco are 2.5v so output have to be 2.5v(no LVTTL will be output ) ?.
Or Input Vcco and Output Vcco are quite different?
I have twenty pairs of LVDS (as input) to connect with PADs of spartan2e and want to output LVTTL with left PADS .
I don't understand about Vcco clearly
I find this in xilinx datasheet about spartan2e (In the TQ144 and PQ208 packages, the eight banks have VCCO connected together.)whether that's means if I select LVDS as IOSTANDARD ,the PADs no matter input or output are all been LDVS ,that is due to Vcco are 2.5v so output have to be 2.5v(no LVTTL will be output ) ?.
Or Input Vcco and Output Vcco are quite different?